China Semiconductor Fabrication: SMIC, Hua Hong, and Domestic Chip Production
China's semiconductor fabrication industry has become one of the world's most critical technology battlegrounds. Despite US export controls restricting access to EUV lithography since 2023, Chinese foundries led by SMIC have made remarkable progress using multi-patterning DUV techniques. China now operates over 200 semiconductor fabs and is building new capacity faster than any other country, driven by massive government investment exceeding 250 billion RMB through the National Integrated Circuit Industry Investment Fund.
TL;DR
SMIC achieved 5nm production using DUV multi-patterning, approximately 3 years behind TSMC. China operates 200+ semiconductor fabs with 50 new fabs under construction. Total domestic fab capacity grew 25% year-over-year. Hua Hong became the world's second-largest pure-play foundry by capacity. YMTC and CXMT remain under US sanctions but continue progressing in mature nodes.
Key Insights
SMIC 5nm Breakthrough
SMIC achieved 5nm-equivalent production using DUV lithography with multi-patterning techniques, producing chips for Huawei's Kirin 9100. Yield rates remain lower than TSMC but are improving rapidly. This represents a 3-year gap with TSMC's leading 3nm process.
Fab Construction Pipeline
China has approximately 50 semiconductor fabs currently under construction, representing 40% of global new fab capacity. SMIC is building new facilities in Beijing, Shanghai, and Shenzhen. Hua Hong is expanding in Wuxi and Shanghai with combined investment of 170 billion RMB.
Domestic Capacity Growth
China's total semiconductor fabrication capacity grew 25% in 2025, reaching approximately 18% of global capacity. The country is expected to surpass Taiwan in total fab capacity by 2026, though not in leading-edge technology. Mature nodes (28nm and above) account for 85% of new capacity.
Equipment Localization
Chinese semiconductor equipment makers now supply approximately 35% of domestic fab equipment needs, up from 20% two years ago. Naura Technology leads in etching, AMEC in cleaning equipment, and Shanghai Micro Electronics Equipment (SMEE) is developing DUV lithography tools. EUV remains a critical gap.
Side-by-Side Comparison
| Company | Technology | Capacity | Key Products | Sanctions Status |
|---|---|---|---|---|
| SMIC | 5nm DUV | 1.2M wafers/month | Huawei Kirin, IoT, automotive | US Entity List since 2020 |
| Hua Hong | 55-28nm | 800K wafers/month | MCU, power, CIS, NOR flash | Not sanctioned |
| YMTC | 232-layer NAND | 150K wafers/month | SSD, enterprise storage | US Entity List since 2022 |
| CXMT | 17nm DRAM | 100K wafers/month | DDR4, LPDDR5 | US Entity List since 2022 |
| Nexchip | 40-28nm | 100K wafers/month | DDI, PMIC, MCU | Not sanctioned |
| GigaDevice | Flash/MCU | N/A (fabless) | NOR flash, 32-bit MCU | Not sanctioned |
Frequently Asked Questions
SMIC achieved 5nm-equivalent production using DUV (deep ultraviolet) lithography with multi-patterning techniques, a significantly more complex and expensive process than EUV: DUV lithography at 193nm wavelength normally supports down to approximately 7nm node, but SMIC uses SAQP (self-aligned quadruple patterning) to effectively quadruple the resolution, achieving transistor densities close to 5nm; the trade-off is significantly lower yield rates (estimated 30-50% vs TSMC's 80%+ for leading-edge nodes) and much higher production costs due to requiring 4x more lithography passes per layer; SMIC also collaborated closely with Huawei's HiSilicon design team to optimize chip layouts for DUV-friendly manufacturing, reducing the number of critical layers requiring multi-patterning; production time per wafer is estimated to be 40-60% longer than comparable EUV-based processes, reducing effective throughput; SMIC has invested heavily in advanced process control and metrology equipment to improve yield consistency, with some reports suggesting yields have improved to 50%+ for production orders; and this approach cannot scale below 5nm, meaning SMIC will eventually need EUV or equivalent technology for 3nm and beyond, which remains blocked by US export controls on ASML EUV systems. While impressive as a workaround, the fundamental limitations mean China's leading-edge chip production will remain more expensive and lower-yield than Taiwan-based manufacturing for the foreseeable future.
China's semiconductor self-sufficiency rate in 2025 is approximately 25-30% by value and 50% by volume: by value, China still imports approximately 70-75% of its semiconductor needs, totaling over 350 billion USD in annual chip imports, making semiconductors China's single largest import category; by volume (number of chips), China produces approximately 50% of its needs, but this is heavily weighted toward mature-node chips used in consumer electronics, automotive, and industrial applications; for leading-edge chips (7nm and below), China's self-sufficiency is less than 5%, with virtually all advanced AI chips, high-performance computing chips, and premium smartphone processors either imported or produced at SMIC with foreign-designed IP cores; the Chinese government's stated goal is to achieve 70% self-sufficiency by 2025 (originally set in 2015), but this target has been widely acknowledged as unachievable in value terms, though the volume target may be within reach; the National Integrated Circuit Industry Investment Fund (Big Fund) has committed approximately 340 billion RMB across three phases, with Phase III (2024) focusing on equipment and materials; and independent analysts estimate that under current trends, China may achieve 40-50% value self-sufficiency by 2030, with the remaining gap primarily in cutting-edge logic chips and specialized semiconductor manufacturing equipment.